System for controlling leakage current in integrated circuits

ABSTRACT

An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.

FIELD OF USE

The present disclosure relates generally to electronic circuits, and,more particularly, to a system for controlling a leakage current inintegrated circuits.

BACKGROUND

In an integrated circuit (IC), dummy transistors are abutted to activetransistors to maximize the mobility of the electrons in the activetransistor. Additionally, the dummy transistors provide a significantimprovement in transistor matching. The dummy transistors areelectrically inactive with gate regions being at the same voltage levelas source regions and/or drain regions. However, such a configuration ofthe dummy transistors creates a voltage difference between the activetransistors and the dummy transistors, and in turn, results in a leakagecurrent between the active transistors and the dummy transistors. Theleakage current degrades the accuracy and the functionality of the IC.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description of the embodiments of the presentdisclosure will be better understood when read in conjunction with theappended drawings. The present disclosure is illustrated by way ofexample, and not limited by the accompanying figures, in which likereferences indicate similar elements.

FIG. 1 illustrates a schematic circuit diagram of an integrated circuit(IC) in accordance with an embodiment of the present disclosure;

FIG. 2 illustrates a layout diagram of the IC of FIG. 1 in accordancewith an embodiment of the present disclosure;

FIG. 3 illustrates a schematic circuit diagram of a frequency-lockedloop in accordance with an embodiment of the present disclosure; and

FIG. 4 illustrates a schematic circuit diagram of dummy transistorsabutted to active transistors of a fine-tuning circuit of thefrequency-locked loop of FIG. 3 in accordance with an embodiment of thepresent disclosure.

DETAILED DESCRIPTION

The detailed description of the appended drawings is intended as adescription of the embodiments of the present disclosure, and is notintended to represent the only form in which the present disclosure maybe practiced. It is to be understood that the same or equivalentfunctions may be accomplished by different embodiments that are intendedto be encompassed within the spirit and scope of the present disclosure.

In an embodiment of the present disclosure, an integrated circuit (IC)is disclosed. The IC may include an active transistor and a plurality ofdummy transistors. The plurality of dummy transistors may be coupled ina series configuration. Each dummy transistor of the plurality of dummytransistors is electrically inactive. Further, a first dummy transistorof the plurality of dummy transistors may include first and secondconductive regions. Similarly, each remaining dummy transistor of theplurality of dummy transistors may include first and second conductiveregions. The first conductive region of the first dummy transistor maybe coupled to the active transistor. Further, the second conductiveregion of the first dummy transistor and the first and second conductiveregions of each remaining dummy transistor of the plurality of dummytransistors are maintained in a floating state to control a leakagecurrent between the active transistor and the plurality of dummytransistors.

In some embodiments, the IC may further include an active diffusionarea. The first and second conductive regions of the first dummytransistor and the first and second conductive regions of each remainingdummy transistor of the plurality of dummy transistors are formed on theactive diffusion area. Further, the first conductive region of oneremaining dummy transistor of the plurality of dummy transistors isformed at an end of the active diffusion area.

In some embodiments, the IC may further include a dielectric isolationregion that may be formed around the active diffusion area to facilitateelectrical isolation of the active diffusion area.

In some embodiments, the leakage current may be further controlled basedon an effective channel length of the plurality of dummy transistors.The effective channel length may be determined based on a number ofdummy transistors of the plurality of dummy transistors.

In some embodiments, each dummy transistor of the plurality of dummytransistors may further include a gate region. The gate region of eachdummy transistor of the plurality of dummy transistors is at a firstvoltage level that renders each dummy transistor of the plurality ofdummy transistors electrically inactive.

In some embodiments, the active transistor may include a firstconductive region that is at a second voltage level. The firstconductive region of the active transistor may be coupled to the firstconductive region of the first dummy transistor. Further, the firstconductive region of the active transistor may be electrically isolatedfrom the second conductive region of the first dummy transistor and thefirst and second conductive regions of each remaining dummy transistorof the plurality of dummy transistors. The leakage current between theactive transistor and the plurality of dummy transistors may becontrolled based on the first conductive region of the active transistorbeing electrically isolated from the second conductive region of thefirst dummy transistor and the first and second conductive regions ofeach remaining dummy transistor of the plurality of dummy transistors.

In some embodiments, the active transistor may further include a gateregion that is at a third voltage level and a second conductive regionthat is at a fourth voltage level. A difference between the thirdvoltage level and one of a group consisting of the second and fourthvoltage levels is greater than a threshold voltage of the activetransistor, thereby rendering the active transistor electrically active.

In another embodiment of the present disclosure, an IC is disclosed. TheIC may include first and second active transistors. The IC may furtherinclude a plurality of dummy transistors that may be coupled in a seriesconfiguration. Each dummy transistor of the plurality of dummytransistors is electrically inactive. First and second dummy transistorsof the plurality of dummy transistors may each include first and secondconductive regions. Further, each remaining dummy transistor of theplurality of dummy transistors may include first and second conductiveregions. The first conductive region of the first dummy transistor maybe coupled to the first active transistor, and the first conductiveregion of the second dummy transistor may be coupled to the secondactive transistor. Further, the second conductive region of the firstdummy transistor, the second conductive region of the second dummytransistor, and the first and second conductive regions of eachremaining dummy transistor of the plurality of dummy transistors aremaintained in a floating state to control a leakage current between thefirst and second active transistors.

In some embodiments, the IC may further include an active diffusionarea. The first and second conductive regions of the first dummytransistor, the first and second conductive regions of the second dummytransistor, and the first and second conductive regions of eachremaining dummy transistor of the plurality of dummy transistors areformed on the active diffusion area.

In some embodiments, each dummy transistor of the plurality of dummytransistors may further include a gate region. The gate region of eachdummy transistor of the plurality of dummy transistors is at a firstvoltage level that renders each dummy transistor of the plurality ofdummy transistors electrically inactive.

In some embodiments, the first active transistor may include a firstconductive region that is at a second voltage level and that is coupledto the first conductive region of the first dummy transistor. The secondactive transistor may include a first conductive region that is at athird voltage level and that is coupled to the first conductive regionof the second dummy transistor. As the second conductive region of thefirst dummy transistor, the second conductive region of the second dummytransistor, and the first and second conductive regions of eachremaining dummy transistor of the plurality of dummy transistors aremaintained in the floating state, the first conductive region of thefirst active transistor is electrically isolated from the firstconductive region of the second active transistor. The leakage currentbetween the first and second active transistors may be controlled basedon the electrical isolation between the first conductive region of thefirst active transistor and the first conductive region of the secondactive transistor.

In some embodiments, the first active transistor may further include agate region that is at a fourth voltage level and a second conductiveregion that is at a fifth voltage level. A difference between the fourthvoltage level and one of a group consisting of the second voltage leveland the fifth voltage level is greater than a threshold voltage of thefirst active transistor, thereby rendering the first active transistorelectrically active.

In some embodiments, the second active transistor may further include agate region that is at a sixth voltage level and a second conductiveregion that is at a seventh voltage level. A difference between thesixth voltage level and one of a group consisting of the third voltagelevel and the seventh voltage level is greater than a threshold voltageof the second active transistor, thereby rendering the second activetransistor electrically active.

In yet another embodiment of the present disclosure, an IC is disclosed.The IC may include a first active transistor and a second activetransistor. The IC may further include a first plurality of dummytransistors that may be coupled in a series configuration. Similarly,the IC may include a second plurality of dummy transistors that may becoupled in the series configuration. First and second dummy transistorsof the first plurality of dummy transistors may each include first andsecond conductive regions. Similarly, a third dummy transistor of thesecond plurality of dummy transistors may include first and secondconductive regions. Further, each remaining dummy transistor of thefirst and second pluralities of dummy transistors may include first andsecond conductive regions. The first conductive region of the firstdummy transistor may be coupled to the first active transistor and thefirst conductive region of the second dummy transistor may be coupled tothe second active transistor. The second conductive region of the firstdummy transistor, the second conductive region of the second dummytransistor, and the first and second conductive regions of eachremaining dummy transistor of the first plurality of dummy transistorsare maintained in a floating state to control a first leakage currentbetween the first active transistor and the second active transistor.Further, the first conductive region of the third dummy transistor maybe coupled to the second active transistor. The second conductive regionof the third dummy transistor and the first and second conductiveregions of each remaining dummy transistor of the second plurality ofdummy transistors are maintained in the floating state to control asecond leakage current between the second active transistor and thesecond plurality of dummy transistors.

Conventionally, to reduce a leakage current generated due to the dummytransistors in an integrated circuit (IC), source and drain regions ofeach dummy transistor are coupled to a conductive region (e.g., a sourceregion or a drain region) of an associated active transistor. Such aconfiguration prevents the creation of a voltage difference between theactive transistor and the dummy transistors, thereby reducing theleakage current therebetween. However, in such an IC, the couplingbetween the dummy transistors and the active transistor results in anincrease in the capacitance at the active transistor, thereby degradingthe operational speed of the active transistor.

Various embodiments of the present disclosure disclose an IC that mayinclude one or more active transistors and multiple dummy transistors.The dummy transistors may be coupled to each other in a seriesconfiguration. Further, the dummy transistors may be coupled between twoactive transistors and/or at the ends of each active transistor. Whenthe dummy transistors are coupled between two active transistors, afirst conductive region of a first dummy transistor and a firstconductive region of a second dummy transistor are coupled to the twoactive transistors, respectively. Further, a second conductive region ofthe first dummy transistor, a second conductive region of the seconddummy transistor, and first and second conductive regions of eachremaining dummy transistor are maintained in a floating state to controla leakage current between the two active transistors. Similarly, whenthe dummy transistors are coupled at an end of an active transistor, afirst conductive region of a third dummy transistor is coupled to theactive transistor. Further, a second conductive region of the thirddummy transistor and first and second conductive regions of eachremaining dummy transistor are maintained in the floating state tocontrol a leakage current between the active transistor and the dummytransistors.

Thus, in the present disclosure, the leakage current is controlled basedon the conductive regions of the dummy transistors being maintained inthe floating state. As a result, the operational speed of the IC of thepresent disclosure is significantly greater than that of an IC where theconductive regions of the dummy transistors are coupled to theconductive region of an active transistor. Additionally, the leakagecurrent in the IC of the present disclosure is significantly less thanthat in an IC where the conductive regions of the dummy transistors areat a ground voltage level or a supply voltage level. Thus, the IC of thepresent disclosure may be implemented in safety-critical applications(e.g., automotive applications).

FIG. 1 illustrates a schematic circuit diagram of an integrated circuit(IC) 100 in accordance with an embodiment of the present disclosure. TheIC 100 may include a first active transistor 102, a second activetransistor 104, a first plurality of dummy transistors 106, a secondplurality of dummy transistors 108, a voltage generator 110, and acontrol circuit 112.

Each of the first and second active transistors 102 and 104 may includea first conductive region, a second conductive region, and a gateregion. A conductive region of a transistor corresponds to a sourceregion or a drain region. For the sake of ongoing discussion, it isassumed that the first and second conductive regions of each of thefirst and second active transistors 102 and 104 correspond to a drainregion and a source region, respectively. The drain, source, and gateregions of the first active transistor 102 may be at first through thirdvoltage levels V1-V3, respectively. Similarly, the drain, source, andgate regions of the second active transistor 104 may be at fourththrough sixth voltage levels V4-V6, respectively. In an embodiment, eachof the first and second active transistors 102 and 104 is an n-channelmetal-oxide-semiconductor (NMOS) transistor. Thus, the first activetransistor 102 is electrically active when a difference between thethird and second voltage levels V3 and V2 is greater than a thresholdvoltage of the first active transistor 102. Similarly, the second activetransistor 104 is electrically active when a difference between thesixth and fifth voltage levels V6 and V5 is greater than a thresholdvoltage of the second active transistor 104.

The first plurality of dummy transistors 106 may include a first dummytransistor 106 a, a second dummy transistor 106 b, and a third dummytransistor 106 c. The first dummy transistor 106 a may include a firstconductive region, a second conductive region, and a gate region.Similarly, each of the second and third dummy transistors 106 b and 106c may include a first conductive region, a second conductive region, anda gate region. For the sake of ongoing discussion, it is assumed thatthe first and second conductive regions of each of the first throughthird dummy transistors 106 a-106 c correspond to a drain region and asource region, respectively. In an embodiment, each of the first throughthird dummy transistors 106 a-106 c is an NMOS transistor.

Each dummy transistor of the first through third dummy transistors 106a-106 c is electrically inactive. For example, the gate region of eachof the first through third dummy transistors 106 a-106 c may be at aground voltage level GND that renders the first through third dummytransistors 106 a-106 c electrically inactive.

The first through third dummy transistors 106 a-106 c may be coupled ina series configuration. Additionally, the first plurality of dummytransistors 106 is coupled between the first and second activetransistors 102 and 104. Thus, the source region (e.g., the secondconductive region) of the first dummy transistor 106 a may be coupled tothe source region (e.g., the second conductive region) of the firstactive transistor 102. Further, the drain region (e.g., the firstconductive region) of the first dummy transistor 106 a may be coupled tothe drain region (e.g., the first conductive region) of the second dummytransistor 106 b. Similarly, the source region (e.g., the secondconductive region) of the second dummy transistor 106 b may be coupledto the source region (e.g., the second conductive region) of the thirddummy transistor 106 c. Further, the drain region (e.g., the firstconductive region) of the third dummy transistor 106 c may be coupled tothe drain region (e.g., the first conductive region) of the secondactive transistor 104.

The drain region of the first dummy transistor 106 a, the drain andsource regions of the second dummy transistor 106 b, and the sourceregion of the third dummy transistor 106 c are maintained in a floatingstate. In such a scenario, the source region of the first activetransistor 102 may be electrically isolated from the drain region of thefirst dummy transistor 106 a and the drain and source regions of eachremaining dummy transistor of the first plurality of dummy transistors106. Consequently, the source region of the first active transistor 102may be electrically isolated from the drain region of the second activetransistor 104. In other words, the creation of a significant voltagedifference between the source region of the first active transistor 102and the drain region of the second active transistor 104 is prevented(e.g., a resistance of the first plurality of dummy transistors 106 issignificant). The electrical isolation results in control (e.g.,reduction or elimination) of a first leakage current IL1 between thefirst and second active transistors 102 and 104. The first leakagecurrent IL1 may correspond to a sub-threshold current passing throughthe first plurality of dummy transistors 106 when the first plurality ofdummy transistors 106 is electrically inactive. Thus, the drain regionof the first dummy transistor 106 a, the drain and source regions of thesecond dummy transistor 106 b, and the source region of the third dummytransistor 106 c are maintained in the floating state to control thefirst leakage current IL1 between the first and second activetransistors 102 and 104.

The first leakage current IL1 may be additionally controlled based on aneffective channel length of the first plurality of dummy transistors106. The effective channel length is determined based on a number ofdummy transistors of the first plurality of dummy transistors 106. Forexample, as the number of dummy transistors of the first plurality ofdummy transistors 106 increases, the first leakage current IL1decreases.

The second plurality of dummy transistors 108 may include a fourth dummytransistor 108 a, a fifth dummy transistor 108 b, and a sixth dummytransistor 108 c. The fourth dummy transistor 108 a may include a firstconductive region, a second conductive region, and a gate region.Similarly, each of the fifth and sixth dummy transistors 108 b and 108 cmay include a first conductive region, a second conductive region, and agate region. For the sake of ongoing discussion, it is assumed that thefirst and second conductive regions of each of the fourth through sixthdummy transistors 108 a-108 c correspond to a drain region and a sourceregion, respectively.

Each dummy transistor of the fourth through sixth dummy transistors 108a-108 c is electrically inactive. In an embodiment, each of the fourththrough sixth dummy transistors 108 a-108 c is an NMOS transistor. Thus,the gate region of each of the fourth through sixth dummy transistors108 a-108 c may be at the ground voltage level GND that renders thefourth through sixth dummy transistors 108 a-108 c electricallyinactive.

The fourth through sixth dummy transistors 108 a-108 c may be coupled inthe series configuration. Additionally, the second plurality of dummytransistors 108 is coupled to the second active transistor 104 in series(e.g., coupled to one end of the second active transistor 104). Thus,the source region (e.g., the second conductive region) of the fourthdummy transistor 108 a may be coupled to the source region (e.g., thesecond conductive region) of the second active transistor 104. Further,the drain region (e.g., the first conductive region) of the fourth dummytransistor 108 a may be coupled to the drain region (e.g., the firstconductive region) of the fifth dummy transistor 108 b. Similarly, thesource region (e.g., the second conductive region) of the fifth dummytransistor 108 b may be coupled to the source region (e.g., the secondconductive region) of the sixth dummy transistor 108 c.

The drain region of the fourth dummy transistor 108 a and the drain andsource regions of each remaining dummy transistor of the secondplurality of dummy transistors 108 are maintained in the floating state.In such a scenario, the source region of the second active transistor104 is electrically isolated from the drain region of the fourth dummytransistor 108 a and the drain and source regions of each remainingdummy transistor of the second plurality of dummy transistors 108. Inother words, the creation of a significant voltage difference betweenthe source region of the second active transistor 104 and the drainregion of the sixth dummy transistor 108 c is prevented (e.g., aresistance of the second plurality of dummy transistors 108 issignificant). The electrical isolation results in the control of asecond leakage current IL2 between the second active transistor 104 andthe second plurality of dummy transistors 108. The second leakagecurrent IL2 may correspond to a sub-threshold current passing throughthe second plurality of dummy transistors 108 when the second pluralityof dummy transistors 108 is electrically inactive. Thus, the drainregion of the fourth dummy transistor 108 a, the drain and sourceregions of the fifth dummy transistor 108 b, and the source and drainregions of the sixth dummy transistor 108 c are maintained in thefloating state to control the second leakage current IL2 between thesecond active transistor 104 and the second plurality of dummytransistors 108.

The second leakage current IL2 may be further controlled based on aneffective channel length of the second plurality of dummy transistors108. The effective channel length is determined based on a number ofdummy transistors of the second plurality of dummy transistors 108. Forexample, as the number of dummy transistors of the second plurality ofdummy transistors 108 increases, the second leakage current IL2decreases.

Although not shown, another plurality of dummy transistors may becoupled to an end of the first active transistor 102 in a manner similarto the coupling of the second plurality of dummy transistors 108 to thesecond active transistor 104.

The voltage generator 110 may be coupled to the first and second activetransistors 102 and 104. The voltage generator 110 may include suitablecircuitry that may be configured to perform one or more operations. Forexample, the voltage generator 110 may be configured to generate avoltage equivalent to the third voltage level V3 and provide thegenerated voltage to the gate region of the first active transistor 102.Similarly, the voltage generator 110 may be further configured togenerate a voltage equivalent to the sixth voltage level V6 and providethe generated voltage to the gate region of the second active transistor104.

The control circuit 112 may be coupled to the first and second activetransistors 102 and 104. The control circuit 112 may include suitablecircuitry that may be configured to perform one or more operations. Forexample, the control circuit 112 may be configured to provide a voltageequivalent to the first voltage level V1 to the drain region of thefirst active transistor 102 and receive a voltage equivalent to thesecond voltage level V2 from the source region of the first activetransistor 102. Similarly, the control circuit 112 may be configured toprovide a voltage equivalent to the fourth voltage level V4 to the drainregion of the second active transistor 104 and receive a voltageequivalent to the fifth voltage level V5 from the source region of thesecond active transistor 104. Thus, the control circuit 112 maycorrespond to any electronic circuit that operates in conjunction with atransistor (e.g., an active transistor).

Variations in the IC 100 of FIG. 1:

In a first variation, each of the first and second pluralities of dummytransistors 106 and 108 may include less than or more than three dummytransistors, without deviating from the scope of the present disclosure.

In a second variation, the first active transistor 102, the secondactive transistor 104, the first plurality of dummy transistors 106, andthe second plurality of dummy transistors 108 may be p-channelmetal-oxide-semiconductor (PMOS) transistors instead of NMOStransistors, without deviating from the scope of the present disclosure.

In a third variation, the first and second conductive regions maycorrespond to source and drain regions, respectively.

In a fourth variation, each of the first and second active transistors102 and 104 and the first and second pluralities of dummy transistors106 and 108 may be stacked transistors.

In a fifth variation, the first leakage current IL1 may be generatedwhen the difference between the third and second voltage levels V3 andV2 is less than the threshold voltage of the first active transistor 102and/or when the difference between the sixth and fifth voltage levels V6and V5 is less than the threshold voltage of the second activetransistor 104. Similarly, the second leakage current IL2 may begenerated when the difference between the sixth and fifth voltage levelsV6 and V5 is less than the threshold voltage of the second activetransistor 104.

FIG. 2 illustrates a layout diagram 200 of the IC 100 in accordance withan embodiment of the present disclosure. The layout diagram of the IC100 (hereinafter referred to as the “IC layout 200”) may include anactive diffusion area 202. The active diffusion area 202 may correspondto a p-type substrate or an n-type substrate. Further, the IC layout 200may include a dielectric isolation region 204 that is formed around theactive diffusion area 202 to facilitate electrical isolation of theactive diffusion area 202.

The IC layout 200 may further include first through ninth impurityregions 206-222 and first through eighth gate electrodes 224-238. Thefirst through ninth impurity regions 206-222 are formed on the activediffusion area 202 and each gate electrode is formed between twoimpurity regions. A gate electrode formed between two impurity regionsresults in the formation of a metal-oxide-semiconductor (MOS)transistor. Thus, the first through ninth impurity regions 206-222 andthe first through eighth gate electrodes 224-238 result in the formationof eight MOS transistors on the active diffusion area 202.

The eight MOS transistors may sequentially correspond to the firstactive transistor 102, the first through third dummy transistors 106a-106 c, the second active transistor 104, and the fourth through sixthdummy transistors 108 a-108 c. Thus, the first through eighth gateelectrodes 224-238 correspond to the gate regions of the first activetransistor 102, the first through third dummy transistors 106 a-106 c,the second active transistor 104, and the fourth through sixth dummytransistors 108 a-108 c, respectively. Further, one impurity region maybe shared between two MOS transistors.

The first and second impurity regions 206 and 208 correspond to thedrain and source regions of the first active transistor 102,respectively. Similarly, the second and third impurity regions 208 and210 correspond to the source and drain regions of the first dummytransistor 106 a, respectively, and the third and fourth impurityregions 210 and 212 correspond to the drain and source regions of thesecond dummy transistor 106 b, respectively. Additionally, the fourthand fifth impurity regions 212 and 214 correspond to the source anddrain regions of the third dummy transistor 106 c, respectively. Thus,the second impurity region 208 corresponds to the source region that isshared between the first active transistor 102 and the first dummytransistor 106 a. Further, the third impurity region 210 corresponds tothe drain region that is shared between the first and second dummytransistors 106 a and 106 b, and the fourth impurity region 212corresponds to the source region that is shared between the second andthird dummy transistors 106 b and 106 c.

The fifth and sixth impurity regions 214 and 216 correspond to the drainand source regions of the second active transistor 104, respectively.Further, the sixth and seventh impurity regions 216 and 218 correspondto the source and drain regions of the fourth dummy transistor 108 a,respectively, and the seventh and eighth impurity regions 218 and 220correspond to the drain and source regions of the fifth dummy transistor108 b, respectively. Similarly, the eighth and ninth impurity regions220 and 222 correspond to the source and drain regions of the sixthdummy transistor 108 c, respectively. Thus, the fifth impurity region214 corresponds to the drain region that is shared between the thirddummy transistor 106 c and the second active transistor 104, and thesixth impurity region 216 corresponds to the source region that isshared between the second active transistor 104 and the fourth dummytransistor 108 a. Further, the seventh impurity region 218 correspondsto the drain region that is shared between the fourth and fifth dummytransistors 108 a and 108 b, and the eighth impurity region 220corresponds to the source region that is shared between the fifth andsixth dummy transistors 108 b and 108 c. Further, the ninth impurityregion 222 is formed at an end of the active diffusion area 202. Inother words, the drain region of the sixth dummy transistor 108 c isformed at an end of the active diffusion area 202.

Although not shown, the IC layout 200 may additionally include impurityregions and gate electrodes corresponding to another plurality of dummytransistors coupled to an end of the first active transistor 102.

The first and second impurity regions 206 and 208 may be at the firstand second voltage levels V1 and V2 and the first gate electrode 224 maybe at the third voltage level V3. Similarly, the fifth and sixthimpurity regions 214 and 216 may be at the fourth and fifth voltagelevels V4 and V5 and the fifth gate electrode 232 may be at the sixthvoltage level V6. Further, the second, third, and fourth gate electrodes226, 228, and 230 are at the ground voltage level GND, and the third andfourth impurity regions 210 and 212 are maintained in the floatingstate. As a result, the first leakage current IL1 between the first andsecond active transistors 102 and 104 is controlled. Similarly, thesixth, seventh, and eighth gate electrodes 234, 236, and 238 are at theground voltage level GND, and the seventh through ninth impurity regions218-222 are maintained in the floating state. As a result, the secondleakage current IL2 between the second active transistor 104 and thesecond plurality of dummy transistors 108 is controlled.

Although not shown, the IC layout 200 may additionally include a layoutof the voltage generator 110 and the control circuit 112.

FIG. 3 illustrates a schematic circuit diagram of a frequency-lockedloop 300 in accordance with an embodiment of the present disclosure. Thefrequency-locked loops (such as the frequency-locked loop 300) may beconfigured to generate clock signals having fixed frequencies, andhence, may be utilized in various electronic applications such as radio,telecommunication devices, computers, or the like. The frequency-lockedloop 300 corresponds to an exemplary circuit in which dummy transistorsare abutted to active transistors in a manner similar to that describedin FIG. 1 to control leakage currents therein. The manner in which dummytransistors are coupled to the active transistors may be utilized invarious other circuits, without deviating from the scope of the presentdisclosure.

The frequency-locked loop 300 may include a first resistor 302 and asecond resistor 304 coupled in series. For example, a first terminal ofthe first resistor 302 may be coupled to a first terminal of the secondresistor 304. Further, a second terminal of the first resistor 302 maybe coupled to a power supply (not shown), and may be configured toreceive a supply voltage VDD. Additionally, a voltage equivalent to aseventh voltage level V7 may be generated at a second terminal of thesecond resistor 304 as a result of a voltage drop across the first andsecond resistors 302 and 304. In an example, resistances of the firstand second resistors 302 and 304 are equal to 150 kilo-ohms (kΩ) and 75kΩ, respectively. The frequency-locked loop 300 may further include afine-tuning circuit 306, a coarse-tuning circuit 308, a controller 310,an amplifier 312, a ring oscillator 314, a level shifter 316, and afrequency-to-voltage converter (F/V converter) 318.

The fine-tuning circuit 306 may include a plurality of activetransistors of which a third active transistor 320 a, a fourth activetransistor 320 b, and a fifth active transistor 320 c are shown.Additionally, the fine-tuning circuit 306 may include a plurality ofresistors of which a third resistor 322 a, a fourth resistor 322 b, anda fifth resistor 322 c are shown. Each of the third through fifthresistors 322 a-322 c may include a first terminal and a secondterminal, and each of the third through fifth active transistors 320a-320 c may include a first conductive region, a second conductiveregion, and a gate region. For the sake of ongoing discussion, it isassumed that the first and second conductive regions of each of thethird through fifth active transistors 320 a-320 c correspond to drainand source regions, respectively.

The first terminal of the third resistor 322 a may be coupled to thesecond terminal of the second resistor 304. In other words, the firstterminal of the third resistor 322 a may be at the seventh voltage levelV7. Further, the plurality of resistors (e.g., the third through fifthresistors 322 a-322 c) may be coupled in the series configuration. Inother words, the second terminal of the third resistor 322 a may becoupled to the first terminal of the fourth resistor 322 b, and thesecond terminal of the fourth resistor 322 b may be coupled to the firstterminal of the fifth resistor 322 c. Further, the source regions of thethird through fifth active transistors 320 a-320 c may be coupled to thesecond terminals of the third through fifth resistors 322 a-322 c,respectively. In such a scenario, voltages equivalent to eighth throughtenth voltage levels V8-V10 may be generated at the source regions ofthe third through fifth active transistors 320 a-320 c as a result ofthe voltage drop across the third through fifth resistors 322 a-322 c,respectively.

The gate regions of the third through fifth active transistors 320 a-320c may be at eleventh through thirteenth voltage levels V11-V13,respectively. Further, the drain regions of the third through fifthactive transistors 320 a-320 c may be coupled to each other and may beat a fourteenth voltage level V14. In an embodiment, each of the thirdthrough fifth active transistors 320 a-320 c corresponds to an NMOStransistor. Thus, the third through fifth active transistors 320 a-320 cmay be electrically active when the voltage differences betweencorresponding gate and source regions are greater than the associatedthreshold voltages. In an embodiment, at any instance, one of the thirdthrough fifth active transistors 320 a-320 c is activated.

The coarse-tuning circuit 308 may be coupled between the fine-tuningcircuit 306 and a ground terminal. The coarse-tuning circuit 308 may beconfigured to receive a voltage equivalent to the fourteenth voltagelevel V14. The coarse-tuning circuit 308 may be structurally similar tothe fine-tuning circuit 306 with the difference being in the resistancevalues of the associated resistors. For example, the resistance value ofeach of the third through fifth resistors 322 a-322 c is equal to 538ohms (Ω), whereas the resistance value of each resistor of thecoarse-tuning circuit 308 is equal to 10.7 kn.

The fine-tuning and coarse-tuning circuits 306 and 308 thus control thegeneration of a reference voltage VREF at the first terminals of thefirst and second resistors 302 and 304. In other words, the referencevoltage VREF may be coarsely tuned by the coarse-tuning circuit 308, andthe fine-tuning of the reference voltage VREF may be executed by thefine-tuning circuit 306. For example, when the third active transistor320 a and one of the active transistors of the coarse-tuning circuit 308are activated, the first through third resistors 302, 304, and 322 a andthe resistors of the coarse-tuning circuit 308 form a voltage dividerthat results in the generation of the reference voltage VREF. The activetransistors of the coarse-tuning circuit 308 may be activated in amanner similar to the activation of the active transistors of thefine-tuning circuit 306.

The controller 310 may be coupled to the fine-tuning circuit 306. Thecontroller 310 may include suitable circuitry that may be configured toperform one or more operations. For example, the controller 310 may beconfigured to generate the voltages equivalent to the eleventh throughthirteenth voltage levels V11-V13 and provide the generated voltages tothe gate regions of the third through fifth active transistors 320 a-320c, respectively.

The amplifier 312 may be coupled to the first terminal of the firstresistor 302 and the F/V converter 318. The amplifier 312 may beconfigured to receive the reference voltage VREF from the first terminalof the first resistor 302. Further, the amplifier 312 may be configuredto receive a feedback voltage VFB from the F/V converter 318. Based onthe reference voltage VREF and the feedback voltage VFB, the amplifier312 may be configured to generate a control voltage VCT. The controlvoltage VCT is an amplified version of a difference between thereference and feedback voltages VREF and VFB. The ring oscillator 314may be coupled to the amplifier 312, and configured to receive thecontrol voltage VCT from the amplifier 312 and generate a first clocksignal CLK1 based on a voltage level of the control voltage VCT. Thelevel shifter 316 may be coupled to the ring oscillator 314, andconfigured to receive the first clock signal CLK1 and execute alevel-shifting operation on the first clock signal CLK1 to generate asecond clock signal CLK2.

The F/V converter 318 may be coupled to the level shifter 316 and theamplifier 312. The F/V converter 318 may be configured to receive thesecond clock signal CLK2 and generate the feedback voltage VFB based onthe frequency of the second clock signal CLK2. The reference voltageVREF and the feedback voltage VFB thus control the frequency of thesecond clock signal CLK2.

Although not shown, the frequency-locked loop 300 may include variousother components (e.g., capacitors, bias circuits, or the like) thatfacilitate the generation of the second clock signal CLK2. Further, inthe frequency-locked loop 300, the first and second resistors 302 and304, the coarse-tuning circuit 308, the third through fifth resistors322 a-322 c, the amplifier 312, the ring oscillator 314, the levelshifter 316, and the F/V converter 318 may correspond to a controlcircuit (such as the control circuit 112) that operates in conjunctionwith the active transistors (e.g., the third through fifth activetransistors 320 a-320 c).

The second clock signal CLK2 corresponds to an output of thefrequency-locked loop 300. When the frequency-locked loop 300 is in alocked state, the frequency of the second clock signal CLK2 is inverselyproportional to a product of resistance and capacitance values of aresistor-capacitor circuit (not shown) utilized in the F/V converter318.

In a conventional frequency-locked loop, dummy transistors are coupledto the active transistors (e.g., the third through fifth activetransistors 320 a-320 c) to maximize the mobility of the electrons inthe active transistors. Typically, the dummy transistors areelectrically inactive with gate regions being at the same voltage levelas the source regions and/or drain regions. Such a configuration of thedummy transistors results in a leakage current between the activetransistors and the dummy transistors. The leakage current offsets areference voltage, especially across temperatures (e.g., as thetemperature increases, the magnitude of the leakage current increasesand the reference voltage is further offset). Such a reference voltagedegrades the accuracy of the clock signal generated by the conventionalfrequency-locked loop. In other words, as a result of the leakagecurrent, the frequency of the clock signal generated by the conventionalfrequency-locked loop may vary more than a tolerance limit of theconventional frequency-locked loop. Such variations in the clock signaldegrade the functionality of the conventional frequency-locked loop.

In the present disclosure (e.g., as illustrated in FIG. 1 ), the dummytransistors that are abutted to the active transistors have floatingstate conductive regions that control a leakage current passingtherethrough. As a result, the leakage current associated with the dummytransistors of the present disclosure is less than that in theconventional frequency-locked loop. Hence, the frequency variations ofthe second clock signal CLK2 are within a tolerance limit of thefrequency-locked loop 300. The coupling of the dummy transistors to thethird through fifth active transistors 320 a-320 c is illustrated inFIG. 4 .

FIG. 4 illustrates a schematic circuit diagram of dummy transistorsabutted to active transistors of the fine-tuning circuit 306 inaccordance with an embodiment of the present disclosure. As described inFIG. 3 , the fine-tuning circuit 306 may include the third through fifthactive transistors 320 a-320 c and the third through fifth resistors 322a-322 c. The fine-tuning circuit 306 may further include third andfourth pluralities of dummy transistors 402 and 404 that are coupled totwo ends (e.g., conductive regions) of the third active transistor 320a, respectively. Similarly, the fine-tuning circuit 306 may furtherinclude fifth and sixth pluralities of dummy transistors 406 and 408that are coupled to two ends (e.g., conductive regions) of the fourthactive transistor 320 b, respectively. Further, the fine-tuning circuit306 may include seventh and eighth pluralities of dummy transistors 410and 412 that are coupled to two ends (e.g., conductive regions) of thefifth active transistor 320 c, respectively.

Each dummy transistor of the third through eighth pluralities of dummytransistors 402-412 may include a first conductive region, a secondconductive region, and a gate region. For the sake of ongoingdiscussion, it is assumed that the first and second conductive regionsof each dummy transistor of the third through eighth pluralities ofdummy transistors 402-412 correspond to drain and source regions,respectively. Further, each dummy transistor of the third through eighthpluralities of dummy transistors 402-412 is electrically inactive. In anembodiment, each dummy transistor of the third through eighthpluralities of dummy transistors 402-412 is an NMOS transistor. Thus,the gate region of each dummy transistor of the third through eighthpluralities of dummy transistors 402-412 may be at the ground voltagelevel GND that renders the third through eighth pluralities of dummytransistors 402-412 electrically inactive.

The third plurality of dummy transistors 402 may include seventh throughninth dummy transistors 402 a-402 c that may be coupled in the seriesconfiguration. The drain region of the seventh dummy transistor 402 amay be coupled to the drain region of the third active transistor 320 a.Further, the source region of the seventh dummy transistor 402 a and thesource and drain regions of the eighth and ninth dummy transistors 402 band 402 c are maintained in the floating state. As a result, the drainregion of the third active transistor 320 a is electrically isolatedfrom the source region of the seventh dummy transistor 402 a and thesource and drain regions of the eighth and ninth dummy transistors 402 band 402 c. Such electrical isolation controls a third leakage currentIL3 between the third active transistor 320 a and the third plurality ofdummy transistors 402. The fourth plurality of dummy transistors 404 mayinclude tenth through twelfth dummy transistors 404 a-404 c that may becoupled in the series configuration. The source region of the tenthdummy transistor 404 a may be coupled to the source region of the thirdactive transistor 320 a. Further, the drain region of the tenth dummytransistor 404 a and the source and drain regions of the eleventh andtwelfth dummy transistors 404 b and 404 c are maintained in the floatingstate to control a fourth leakage current IL4 between the third activetransistor 320 a and the fourth plurality of dummy transistors 404.Further, the third plurality of dummy transistors 402, the third activetransistor 320 a, and the fourth plurality of dummy transistors 404 maybe formed on a single active diffusion area (such as the activediffusion area 202).

The fifth plurality of dummy transistors 406 may include thirteenth,fourteenth, and fifteenth dummy transistors 406 a, 406 b, and 406 c thatmay be coupled in the series configuration. Similarly, the sixthplurality of dummy transistors 408 may include sixteenth, seventeenth,and eighteenth dummy transistors 408 a, 408 b, and 408 c that may becoupled in the series configuration. Further, the fifth and sixthpluralities of dummy transistors 406 and 408 may be coupled to the drainand source regions of the fourth active transistor 320 b in a similarmanner as the third and fourth pluralities of dummy transistors 402 and404 are coupled to the third active transistor 320 a, respectively. Thefifth and sixth pluralities of dummy transistors 406 and 408 controlfifth and sixth leakage currents IL5 and IL6 associated with the fourthactive transistor 320 b, respectively, in a similar manner as describedabove. Additionally, the fifth plurality of dummy transistors 406, thefourth active transistor 320 b, and the sixth plurality of dummytransistors 408 may be formed on a single active diffusion area (such asthe active diffusion area 202).

The seventh plurality of dummy transistors 410 may include nineteenth,twentieth, and twenty-first dummy transistors 410 a, 410 b, and 410 cthat may be coupled in the series configuration. Similarly, the eighthplurality of dummy transistors 412 may include twenty-second,twenty-third, and twenty-fourth dummy transistors 412 a, 412 b, and 412c that may be coupled in the series configuration. Further, the seventhand eighth pluralities of dummy transistors 410 and 412 may be coupledto the drain and source regions of the fifth active transistor 320 c ina similar manner as the third and fourth pluralities of dummytransistors 402 and 404 are coupled to the third active transistor 320a, respectively. The seventh and eighth pluralities of dummy transistors410 and 412 control seventh and eighth leakage currents IL7 and IL8associated with the fifth active transistor 320 c, respectively, in asimilar manner as described above. Additionally, the seventh pluralityof dummy transistors 410, the fifth active transistor 320 c, and theeighth plurality of dummy transistors 412 may be formed on a singleactive diffusion area (such as the active diffusion area 202).

Although not shown, the layout diagram of the frequency-locked loop 300may be similar to the IC layout 200 illustrated in FIG. 2 .

The frequency-locked loop 300 illustrated in FIGS. 3 and 4 describe theabutment of the dummy transistors to the ends of one active transistor.However, in various other circuits, the dummy transistors may be coupledbetween two active transistors as described in FIG. 1 , withoutdeviating from the scope of the present disclosure.

Although it is described that dummy transistors are abutted to theactive transistors of the fine-tuning circuit 306, the scope of thepresent disclosure is not limited to it. In various other embodiments,the dummy transistors may be abutted to the active transistors of thecoarse-tuning circuit 308 in a similar manner, without deviating fromthe scope of the present disclosure.

Conventionally, to reduce a leakage current observed in the dummytransistors of an integrated circuit (IC), source and drain regions ofeach dummy transistor are coupled to a conductive region (e.g., a sourceregion or a drain region) of an active transistor. Such a configurationprevents the creation of a voltage difference between the activetransistor and the dummy transistors, thereby reducing the leakagecurrent therebetween. However, in such an IC, the coupling between thedummy transistors and the active transistor results in an increase inthe capacitance at the active transistor, thereby degrading theoperational speed of the active transistor.

In the present disclosure, the dummy transistors having floating sourceand drain regions control the leakage current. As a result, theoperational speed of the IC 100 is significantly greater than that of anIC where the source and drain regions of the dummy transistors arecoupled to the source/drain region of an active transistor.Additionally, the leakage current in the IC 100 is significantly lessthan that in an IC where the source and drain regions of the dummytransistors are at a ground voltage level or a supply voltage level. TheIC 100 may thus be implemented in safety-critical applications (e.g.,automotive applications).

While various embodiments of the present disclosure have beenillustrated and described, it will be clear that the present disclosureis not limited to these embodiments only. Numerous modifications,changes, variations, substitutions, and equivalents will be apparent tothose skilled in the art, without departing from the spirit and scope ofthe present disclosure, as described in the claims. Further, unlessstated otherwise, terms such as “first” and “second” are used toarbitrarily distinguish between the elements such terms describe. Thus,these terms are not necessarily intended to indicate temporal or otherprioritization of such elements.

1. An integrated circuit (IC), comprising: an active transistor; and aplurality of dummy transistors that is coupled in a seriesconfiguration, wherein each dummy transistor of the plurality of dummytransistors is electrically inactive, wherein a first dummy transistorof the plurality of dummy transistors comprises (i) a first conductiveregion that is coupled to the active transistor and (ii) a secondconductive region, wherein each remaining dummy transistor of theplurality of dummy transistors comprises a first conductive region and asecond conductive region, and wherein (i) the second conductive regionof the first dummy transistor and (ii) the first conductive region andthe second conductive region of each remaining dummy transistor of theplurality of dummy transistors are maintained in a floating state tocontrol a leakage current between the active transistor and theplurality of dummy transistors.
 2. The IC of claim 1, further comprisingan active diffusion area, wherein the first conductive region and thesecond conductive region of the first dummy transistor and the firstconductive region and the second conductive region of each remainingdummy transistor of the plurality of dummy transistors are formed on theactive diffusion area, and wherein the first conductive region of oneremaining dummy transistor of the plurality of dummy transistors isformed at an end of the active diffusion area.
 3. The IC of claim 2,further comprising a dielectric isolation region that is formed aroundthe active diffusion area to facilitate electrical isolation of theactive diffusion area.
 4. The IC of claim 1, wherein the leakage currentis further controlled based on an effective channel length of theplurality of dummy transistors, and wherein the effective channel lengthis determined based on a number of dummy transistors of the plurality ofdummy transistors.
 5. The IC of claim 1, wherein each dummy transistorof the plurality of dummy transistors further comprises a gate region,and wherein the gate region of each dummy transistor of the plurality ofdummy transistors is at a first voltage level that renders each dummytransistor of the plurality of dummy transistors electrically inactive.6. The IC of claim 1, wherein the active transistor comprises a firstconductive region that is at a second voltage level, wherein the firstconductive region of the active transistor is coupled to the firstconductive region of the first dummy transistor, and is electricallyisolated from the second conductive region of the first dummy transistorand the first conductive region and the second conductive region of eachremaining dummy transistor of the plurality of dummy transistors, andwherein the leakage current between the active transistor and theplurality of dummy transistors is controlled based on the electricalisolation between (i) the first conductive region of the activetransistor and (ii) the second conductive region of the first dummytransistor and the first conductive region and the second conductiveregion of each remaining dummy transistor of the plurality of dummytransistors.
 7. The IC of claim 6, wherein the active transistor furthercomprises (i) a gate region that is at a third voltage level and (ii) asecond conductive region that is at a fourth voltage level, and whereina difference between the third voltage level and one of a groupconsisting of the second voltage level and the fourth voltage level isgreater than a threshold voltage of the active transistor, therebyrendering the active transistor electrically active.
 8. An integratedcircuit (IC), comprising: a first active transistor and a second activetransistor; and a plurality of dummy transistors coupled in a seriesconfiguration, wherein each dummy transistor of the plurality of dummytransistors is electrically inactive, wherein a first dummy transistorof the plurality of dummy transistors comprises (i) a first conductiveregion that is coupled to the first active transistor and (ii) a secondconductive region, wherein a second dummy transistor of the plurality ofdummy transistors comprises (i) a first conductive region that iscoupled to the second active transistor and (ii) a second conductiveregion, wherein each remaining dummy transistor of the plurality ofdummy transistors comprises a first conductive region and a secondconductive region, and wherein (i) the second conductive region of thefirst dummy transistor, (ii) the second conductive region of the seconddummy transistor, and (iii) the first conductive region and the secondconductive region of each remaining dummy transistor of the plurality ofdummy transistors are maintained in a floating state to control aleakage current between the first active transistor and the secondactive transistor.
 9. The IC of claim 8, further comprising an activediffusion area, wherein the first conductive region and the secondconductive region of the first dummy transistor, the first conductiveregion and the second conductive region of the second dummy transistor,and the first conductive region and the second conductive region of eachremaining dummy transistor of the plurality of dummy transistors areformed on the active diffusion area.
 10. The IC of claim 9, furthercomprising a dielectric isolation region that is formed around theactive diffusion area to facilitate electrical isolation of the activediffusion area.
 11. The IC of claim 8, wherein the leakage current isfurther controlled based on an effective channel length of the pluralityof dummy transistors, and wherein the effective channel length isdetermined based on a number of dummy transistors of the plurality ofdummy transistors.
 12. The IC of claim 8, wherein each dummy transistorof the plurality of dummy transistors further comprises a gate region,and wherein the gate region of each dummy transistor of the plurality ofdummy transistors is at a first voltage level that renders each dummytransistor of the plurality of dummy transistors electrically inactive.13. The IC of claim 8, wherein the first active transistor comprises afirst conductive region that is at a second voltage level and that iscoupled to the first conductive region of the first dummy transistor,wherein the second active transistor comprises a first conductive regionthat is at a third voltage level and that is coupled to the firstconductive region of the second dummy transistor, wherein as the secondconductive region of the first dummy transistor, the second conductiveregion of the second dummy transistor, and the first conductive regionand the second conductive region of each remaining dummy transistor ofthe plurality of dummy transistors are maintained in the floating state,the first conductive region of the first active transistor iselectrically isolated from the first conductive region of the secondactive transistor, and wherein the leakage current between the firstactive transistor and the second active transistor is controlled basedon the electrical isolation between the first conductive region of thefirst active transistor and the first conductive region of the secondactive transistor.
 14. The IC of claim 13, wherein the first activetransistor further comprises (i) a gate region that is at a fourthvoltage level and (ii) a second conductive region that is at a fifthvoltage level, and wherein a difference between the fourth voltage leveland one of a group consisting of the second voltage level and the fifthvoltage level is greater than a threshold voltage of the first activetransistor, thereby rendering the first active transistor electricallyactive.
 15. The IC of claim 13, wherein the second active transistorfurther comprises (i) a gate region that is at a sixth voltage level and(ii) a second conductive region that is at a seventh voltage level, andwherein a difference between the sixth voltage level and one of a groupconsisting of the third voltage level and the seventh voltage level isgreater than a threshold voltage of the second active transistor,thereby rendering the second active transistor electrically active. 16.An integrated circuit (IC), comprising: (i) a first active transistor,(ii) a second active transistor, (iii) a first plurality of dummytransistors that is coupled in a series configuration, and (iv) a secondplurality of dummy transistors that is coupled in the seriesconfiguration, wherein a first dummy transistor of the first pluralityof dummy transistors comprises (i) a first conductive region coupled tothe first active transistor and (ii) a second conductive region, and asecond dummy transistor of the first plurality of dummy transistorscomprises (i) a first conductive region that is coupled to the secondactive transistor and (ii) a second conductive region, wherein a thirddummy transistor of the second plurality of dummy transistors comprises(i) a first conductive region coupled to the second active transistorand (ii) a second conductive region, wherein each remaining dummytransistor of the first plurality of dummy transistors and the secondplurality of dummy transistors comprises a first conductive region and asecond conductive region, wherein (i) the second conductive region ofthe first dummy transistor, (ii) the second conductive region of thesecond dummy transistor, and (iii) the first conductive region and thesecond conductive region of each remaining dummy transistor of the firstplurality of dummy transistors are maintained in a floating state tocontrol a first leakage current between the first active transistor andthe second active transistor, and wherein (i) the second conductiveregion of the third dummy transistor and (ii) the first conductiveregion and the second conductive region of each remaining dummytransistor of the second plurality of dummy transistors are maintainedin the floating state to control a second leakage current between thesecond active transistor and the second plurality of dummy transistors.17. The IC of claim 16, further comprising an active diffusion area,wherein (i) the first conductive region and the second conductive regionof the first dummy transistor, (ii) the first conductive region and thesecond conductive region of the second dummy transistor, (iii) the firstconductive region and the second conductive region of the third dummytransistor, (iv) the first conductive region and the second conductiveregion of each remaining dummy transistor of the first plurality ofdummy transistors, and (v) the first conductive region and the secondconductive region of each remaining dummy transistor of the secondplurality of dummy transistors are formed on the active diffusion area,and wherein the first conductive region of one remaining dummytransistor of the second plurality of dummy transistors is formed at anend of the active diffusion area.
 18. The IC of claim 16, wherein eachdummy transistor of the first plurality of dummy transistors and thesecond plurality of dummy transistors further comprises a gate region,and wherein the gate region of each dummy transistor of the firstplurality of dummy transistors and the second plurality of dummytransistors is at a first voltage level that renders each dummytransistor of the first plurality of dummy transistors and the secondplurality of dummy transistors electrically inactive.
 19. The IC ofclaim 16, wherein the first active transistor comprises a firstconductive region that is at a second voltage level and that is coupledto the first conductive region of the first dummy transistor, whereinthe second active transistor comprises a first conductive region that isat a third voltage level and that is coupled to the first conductiveregion of the second dummy transistor, wherein as the second conductiveregion of the first dummy transistor, the second conductive region ofthe second dummy transistor, and the first conductive region and thesecond conductive region of each remaining dummy transistor of the firstplurality of dummy transistors are maintained in the floating state, thefirst conductive region of the first active transistor is electricallyisolated from the first conductive region of the second activetransistor, and wherein the first leakage current between the firstactive transistor and the second active transistor is controlled basedon the electrical isolation between the first conductive region of thefirst active transistor and the first conductive region of the secondactive transistor.
 20. The IC of claim 19, wherein the second activetransistor further comprises a second conductive region that is at afourth voltage level, wherein the second conductive region of the secondactive transistor is coupled to the first conductive region of the thirddummy transistor, and is electrically isolated from the secondconductive region of the third dummy transistor and the first conductiveregion and the second conductive region of each remaining dummytransistor of the second plurality of dummy transistors, and wherein thesecond leakage current between the second active transistor and thesecond plurality of dummy transistors is controlled based on theelectrical isolation between (i) the second conductive region of thesecond active transistor and (ii) the second conductive region of thethird dummy transistor and the first conductive region and the secondconductive region of each remaining dummy transistor of the secondplurality of dummy transistors.